Method for removing silicon oxide and integrated circuit manufacturing process

ABSTRACT

A method for removing silicon oxide from a wafer and an integrated circuit manufacturing process are provided. The method includes: introducing a dehydrated hydrogen fluoride gas and a dehydrated alcohol gas into a process chamber; mixing the dehydrated hydrogen fluoride gas with the dehydrated alcohol gas to generate gaseous etchants; allowing reactions between the etchants and the wafer in the process chamber under a high pressure maintained in the process chamber to improve an etching selectivity; and pumping out reaction products from the process chamber.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of InternationalApplication No. PCT/CN2017/105369, filed on Oct. 9, 2017, which claimspriority of Chinese Patent Application No. 201610879096.2, filed on Oct.8, 2016, the entire content of all of which is incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates to the field of integrated circuitmanufacturing process and, more particularly, relates to a method forremoving silicon oxide from a wafer in an integrated circuitmanufacturing process and an integrated circuit manufacturing processusing the method.

BACKGROUND

In the field of integrated circuit manufacturing process, integratedcircuits are currently manufactured using silicon-based materials. Whensilicon (or polysilicon) is placed in air, the surface is naturallyoxidized to form a dense layer of silicon oxide (SiO₂), as shown in FIG.1A. In some processes, for example, in a metal silicide process, a metalnickel-platinum (NiPt) film is in direct contact with a substrate of thesilicon-based material. If a layer of SiO₂ is on a surface of thesubstrate, the resistivity may be increased, which may affect deviceperformance, so it is necessary to remove the layer of SiO₂ before asubsequent manufacturing process. While removing the layer of SiO₂,other films or structures must be protected from being removed ordamaged. As shown in FIG. 1A, the linewidth of a spacer (made of siliconnitride (Si₃N₄)) may affect the device's electrical properties, such asleakage etc. Therefore, it is necessary to keep the spacer (Si₃N₄) frombeing removed while removing SiO₂.

As shown in FIG. 1B, the conventional processes mostly use a wet etchingprocess, a plasma dry etching process, etc. to remove SiO₂, which mayhave a low etching selectivity to Si₃N₄ and may remove excessive spacer,thereby reducing the spacer size, increasing leakage and affectingdevice performance.

Therefore, it is necessary to develop a method with high selectivity andhigh efficiency for removing silicon oxide from a wafer, which may beapplied to an integrated circuit manufacturing process.

SUMMARY

One aspect of the present disclosure provides a method for removingsilicon oxide from a wafer. The method includes: introducing adehydrated hydrogen fluoride gas and a dehydrated alcohol gas into aprocess chamber; mixing the dehydrated hydrogen fluoride gas with thedehydrated alcohol gas to generate gaseous etchants; allowing reactionsbetween the etchants and the wafer in the process chamber under a highpressure maintained in the process chamber to improve an etchingselectivity; and pumping out reaction products from the process chamber.

Another aspect of the present disclosure provides an integrated circuitmanufacturing process. The integrated circuit manufacturing processincludes removing silicon oxide from a wafer by a removal method. Theremoval method includes introducing a dehydrated hydrogen fluoride gasand a dehydrated alcohol gas into a process chamber; mixing thedehydrated hydrogen fluoride gas with the dehydrated alcohol gas togenerate gaseous etchants; allowing reactions between the etchants andthe wafer in the process chamber under a high pressure maintained in theprocess chamber to improve an etching selectivity; and pumping outreaction products from the process chamber.

Other aspects or embodiments of the present disclosure can be understoodby professionals skilled in the art in light of the description, theclaims, and the drawings of the present disclosure.

DESCRIPTION OF THE DRAWINGS

The following drawings are merely for illustrative purposes according tovarious embodiments and are not intended to limit the scope of thepresent disclosure.

To more clearly describe the above-mentioned and other objectives,technical solutions and advantages of the present disclosure, thepresent disclosure is further illustrated in detail with reference tothe accompanying drawings in conjunction with embodiments. In theexemplary embodiments of the present disclosure, same reference numeralsgenerally denote some components.

FIG. 1A illustrates a schematic of an integrated circuit device having anative oxide layer;

FIG. 1B illustrates a schematic of an effect of removing silicon oxideaccording to a method of the conventional technology;

FIG. 2 illustrates a flow chart corresponding to certain stages of anexemplary method for removing silicon oxide from a wafer according tovarious disclosed embodiments of the present disclosure;

FIG. 3 illustrates a schematic of an effect of removing silicon oxidefrom a wafer according to various disclosed embodiments of the presentdisclosure;

FIGS. 4A, 4B and 4C respectively illustrate schematics of profilemodification of STI (shallow trench isolation) HARP (high aspect ratioprocess) gap-fill deposition according to the conventional technology;

FIGS. 5A, 5B, 5C, and 5D respectively illustrate schematics of effectsof removing silicon oxide from a wafer in profile modification of STIHARP gap-fill deposition according to various disclosed embodiments ofthe present disclosure;

FIGS. 6A and 6B respectively illustrate schematics of a device having anative oxide layer and a device after removing the native oxide layeraccording to various disclosed embodiments of the present disclosure;

FIGS. 7A and 7B respectively illustrate schematics of a device having apad oxide layer and a device after removing the pad oxide layeraccording to various disclosed embodiments of the present disclosure;

FIGS. 8A and 8B respectively illustrate schematics of a device having anative oxide layer and a device after removing the native oxide layeraccording to various disclosed embodiments of the present disclosure;and

FIGS. 9A and 9B respectively illustrate schematics of an integratedcircuit device having oxide recesses and an effect of removing siliconoxide of a device according to various disclosed embodiments of thepresent disclosure.

DETAILED DESCRIPTION

The present disclosure is described in detail below with reference tothe accompanying drawings. Although the preferred embodiments of thepresent disclosure are shown in the drawings, it should be understoodthat the present disclosure may be embodied in various forms and notlimited by the embodiments set forth herein. Instead, the embodimentsare provided to make the present disclosure more thorough and complete,and the scope of the present disclosure may be fully conveyed to thoseskilled in the art.

A method and a manufacturing process for removing silicon oxide from awafer are provided. The method includes: introducing a dehydratedhydrogen fluoride gas and a dehydrated alcohol gas into a processchamber; mixing the dehydrated hydrogen fluoride gas with the dehydratedalcohol gas to generate gaseous etchants; allowing reactions between theetchants and the wafer in the process chamber under a high pressuremaintained in the process chamber to improve an etching selectivity; andpumping out reaction products from the process chamber.

FIG. 2 illustrates a flow chart corresponding to certain stages of anexemplary method for removing silicon oxide from a wafer according tovarious disclosed embodiments of the present disclosure.

In one embodiment, the method for removing silicon oxide from the waferaccording to the present disclosure may include: step 201, where adehydrated hydrogen fluoride gas and a dehydrated alcohol gas may beintroduced into a process chamber; step 202, where the dehydratedhydrogen fluoride gas may be mixed with the dehydrated alcohol gas togenerate gaseous etchants; step 203, where the etchants may be reactedwith substances to-be-removed such as silicon oxide from the surface ofthe wafer in the process chamber, and the process chamber may bemaintained at a high pressure to increase an etching selectivity; andstep 204, where reaction products may be pumped out from the processchamber.

In one embodiment, gaseous etchants may directly react with siliconoxide under high pressure and the reaction products may be pumped outafter the reaction is completed, which may remove silicon oxide withhigh selectivity and high efficiency.

The method for removing silicon oxide from the wafer according to thepresent disclosure are described in detail hereafter.

In one embodiment, the substance to-be-removed on the wafer surface maybe silicon oxide. The method for removing silicon oxide from the waferaccording to the present disclosure may include: step 201, where thedehydrated hydrogen fluoride gas and the dehydrated alcohol gas may beintroduced into the process chamber; step 202, where the dehydratedhydrogen fluoride gas may be mixed with the dehydrated alcohol gas togenerate gaseous etchants; step 203, where the etchants may be reactedwith silicon oxide from the surface of the wafer in the process chamber,and the process chamber may be maintained at a high pressure to increasethe etching selectivity; and step 204, where the reaction products maybe pumped out from the process chamber.

Optionally, the reaction conditions may include a pressure in theprocess chamber of about 30 torr to 300 torr and a temperature in theprocess chamber of about 20° C. to 80° C. Furthermore, the reactionconditions may include the pressure in the process chamber of about 200torr and the temperature in the process chamber of about 40° C. Thehigher the pressure is in the process chamber in the range of about 30torr to 300 torr, the easier the gaseous etchants (reaction gases) maycondense on the surface of the wafer and react with SiO₂. In such way,the removal rate of SiO₂ may increase greatly, but the removal rate ofSi₃N₄ may not increase at the same time, which may greatly increase theremoval selectivity ratio (e.g., etching selectivity) of SiO₂ to Si₃N₄(or polysilicon, HARP deposition, etc.).

Optionally, a flow rate of the hydrogen fluoride gas may be about 100sccm to 500 sccm and a flow rate of the alcohol gas may be about 100sccm to 1000 sccm. Furthermore, the flow rate of the hydrogen fluoridegas may be about 150 sccm to 225 sccm and the flow rate of the alcoholgas may be about 200 sccm to 450 sccm.

Optionally, the ratio of the flow rate of the hydrogen fluoride gas tothe flow rate of the alcohol gas may be about (0.8-1.2):1. For example,the ratio of the flow rate of the hydrogen fluoride gas to the flow rateof the alcohol gas may be about 0.8:1, 1:1 or 1.2:1. Furthermore, theratio of the flow rate of the hydrogen fluoride gas to the flow rate ofthe alcohol gas may be about 1:1. By making the flow rates of thehydrogen fluoride gas and the alcohol gas similar, the uniformity ofremoving silicon oxide may be improved.

Optionally, the alcohol gas may be at least one of C1 to C8 monohydricalcohol gases. Furthermore, the alcohol gas may be at least one ofmethanol (CH₃OH), ethanol (C₂H₅OH), and isopropyl alcohol (IPA).

When the alcohol gas is vaporized methanol, the etchants are HF₂ ⁻ andCH₃OH₂ ⁺ and the reaction products are silicon tetrafluoride, methanol,and water. When methanol (CH₃OH) is used, the reaction formula of themethod for removing silicon oxide from the wafer according to thepresent disclosure may be expressed as:HF+CH₃OH→HF₂ ⁻+CH₃OH₂ ⁺  (1)HF₂ ⁻+CH₃OH₂ ⁺+SiO₂→SiF₄+CH₃OH+H₂O  (2)

The dehydrated HF gas and the dehydrated CH₃OH gas may be mixed insidethe chamber to generate gaseous etchants HF₂ ⁻+CH₃OH₂ ⁺. The pressure inthe process chamber may be set to about 200 torr and the temperature inthe chamber may be about 40° C. Mixed HF₂ ⁻ and CH₃OH₂ ⁺ may react withSiO₂ to generate SiF₄, CH₃OH and H₂O. CH₃OH may have strong waterabsorption, which may reduce the H₂O residual on the wafer surface.Meanwhile, the reaction products such as SiF₄, CH₃OH and H₂O may bepumped out after the reaction is completed.

In practical applications, the process chamber used in the method forremoving silicon oxide from the wafer according to the presentdisclosure may be integrated with a subsequent process on a vacuumplatform. In such way, after removing the SiO₂ on the wafer surface, thesubsequent process may be performed without damaging the vacuumenvironment, and the wafer may be prevented from being re-oxidized in anon-vacuum environment again before proceeding to the subsequentprocess, which may affect the subsequent process. For example, thevacuum environment may be maintained for the subsequent process,including deposition of platinum-nickel (NiPt) and/or silicon germanium(SiGe) for forming the silicide.

The advantages of the method for removing silicon oxide from the waferaccording to the present disclosure are the following.

1) The selectivity may be high. The selectivity of the presentdisclosure may be improved by a high-pressure process. When thehigh-pressure process (e.g., the process pressure of about 200 torr) isused, the gaseous etchants may be more likely to condense on the surfaceof the wafer and react with SiO₂. In such way, the removal rate of SiO₂may increase greatly, but the removal rate of Si₃N₄ may not increase,thereby increasing the removal rate of SiO₂ and reducing the damage tothe substrate. That is, the method provided by the present disclosuremay greatly increase the removal selectivity ratio of SiO₂ to Si₃N₄ (orpolysilicon, HARP deposition, etc.).

2) Plasma may not be used, and other by-products may not be easy togenerate, which may not damage the substrate, and may reduce particlecontamination, keep the chamber clean, and also reduce equipment costs.

3) SiO₂ may be removed by a chemical reaction. Since there are no solidreaction products, the reaction products may be pumped out. FIGS. 5A and5B illustrate other schematics of effects of removing silicon oxide fromthe wafer according to the present disclosure. As shown in FIGS. 5A-5D,since the reaction products diffuse well, the removal amount of SiO₂ insmall voids in a dense region and in a sparse region may be consistent,and the reaction products such as gaseous SiF₄ may be easily pumped out,which may not cause the small voids to be clogged, may have a good andhigh cleaning effect on the small voids and also a high removaluniformity. Moreover, the method provided in the embodiments of thepresent disclosure may also improve the loading effect of the pad oxidelayer removal and the STI recess etching, so the trench depths of largeand small voids may be etched consistently and the STI heights may bealso consistent. Furthermore, CH₃OH and H₂O may also be easily pumpedout, which may not condense on the chamber wall and may have lessparticles.

4) The method for removing silicon oxide from the wafer provided byembodiments of the present disclosure may have a low processtemperature, such as about 20° C. to 80° C., so high temperature heatingmay not be required, and a cooling step corresponding to the hightemperature step may not be required accordingly. In such way, thereaction process may be simple, and the reaction may be completed in onestep, which may not only improve the process efficiency and capacity,but also at least save the cost generated by the heating step and thecooling step.

In accordance with another aspect of the present disclosure, anintegrated circuit manufacturing process may also be provided, and themanufacturing process may include the above-mentioned methods forremoving silicon oxide from the wafer.

The integrated circuit manufacturing process provided by the presentdisclosure may use the above-mentioned methods provided by theembodiments of the present disclosure to remove silicon oxide from thewafer. Therefore, compared with integrated circuit manufacturingprocesses in the conventional technology using a wet etching process ora plasma etching process to remove silicon oxide, the integrated circuitmanufacturing process provided by the present disclosure may alsoimprove the removal efficiency of silicon oxide, reduce the damage tothe substrate, keep the chamber clean, reduce or even eliminate theparticle contamination caused by the reaction products, and may alsohave the characteristics of simple reaction processes, high processefficiency and capacity, low costs, etc.

To facilitate understanding of the aspects and effects of the presentdisclosure, various embodiments are described hereafter. It should beunderstood by those skilled in the art that embodiments are only forfacilitating understanding of the present disclosure and any specificdetails are not intended to limit the present disclosure.

Embodiment 1: Profile Modification of STI HARP Gap-Fill Deposition

FIGS. 4A, 4B and 4C respectively illustrate schematics of profilemodification of STI HARP gap-fill deposition according to theconventional technology. FIG. 4A illustrates a device after STIstructure etching. FIG. 4B illustrates the device during the STI HARPdeposition. FIG. 4C illustrates the device with generated voids afterthe STI HARP deposition. As shown in FIGS. 4A, 4B and 4C, the STI HARPdeposition may use a chemical vapor deposition (CVD) process. Due to alarge aspect ratio of 28 nm STI structure and a poor profile of STIstructure etching, voids may be easily generated during the STI HARPdeposition. The conventional technology used in FIGS. 4A, 4B, and 4C mayproduce solid reaction products, and have low cleaning efficiency forsmall voids and low capacity.

In one embodiment, the integrated circuit manufacturing process mayinclude a sub-process for a profile modification of a STI HARP gap-filldeposition. The sub-process may include performing an HARP deposition bya CVD process for forming a STI structure having a certain thickness;etching the STI structure having the certain thickness to provide anenlarged opening; and repeatedly performing the HARP deposition and theetching of the STI structure in the enlarged opening, till a completeSTI structure is formed, where the etching of the STI structure includesthe method for removing silicon oxide.

FIGS. 5A, 5B and 5C respectively illustrate schematics of effects ofremoving silicon oxide from a wafer in profile modification of STI HARPgap-fill deposition according to various disclosed embodiments of thepresent disclosure. FIG. 5A illustrates a device after STI structureetching. FIG. 5B illustrates the device during the STI HARP deposition.FIG. 5C illustrates the device with STI structure opening adjustmentusing the method for removing silicon oxide from the wafer of thepresent disclosure. FIG. 5D illustrates the device after the STI HARPdeposition.

In one embodiment, the method for removing silicon oxide from the waferaccording to the present disclosure may be described hereafter. Thedehydrated HF gas and the dehydrated CH₃OH gas may be mixed to generategaseous etchants HF₂ ⁻ and CH₃OH₂ ⁺. Then etchants may be introducedinto the process chamber, and react with SiO₂ on the surface of thewafer in the process chamber to generate SiF₄, CH₃OH and H₂O, where theprocess conditions in the process chamber are: the pressure in thechamber setting to about 200 torr and the temperature in the chamber ofabout 40° C. SiF₄, CH₃OH and H₂O may be pumped out after the reaction iscompleted.

As shown in FIGS. 5A, 5B, 5C, and 5D, in the integrated circuitmanufacturing process provided by the embodiments of the presentdisclosure, the STI structure may be etched to make the opening largerafter depositing a certain thickness of HARP deposition (depositing alayer of SiO2) by a CVD process, which may avoid generating voids. Usingthe method of the present disclosure to remove SiO₂, the non-solidreaction products may be easily pumped out, which may keep the chamberclean, and reduce or even eliminate the particle contamination caused bythe reaction products. The method provided in the embodiments may notrequire high temperature heating, have a simple reaction process, andhave the characteristics of high process efficiency, high processcapacity and low costs. Furthermore, the method provided by the presentdisclosure may have the process pressure of about 200 torr and theprocess temperature of about 40° C., thereby improving the etchingselectivity of SiO₂ to HARP deposition, etc. In such way, the removalefficiency of silicon oxide from the wafer may be improved and thedamage to the substrate may be reduced, thereby controlling the openingprofile and increasing the filling ability of the CVD HARP gap.

Embodiment 2: STI Structure Si₃N₄ Native Oxide Layer Removal

In one embodiment, the integrated circuit manufacturing process mayinclude a sub-process for removing a SiO₂ native oxide layer formed on ahard mask layer of a STI structure, where the mask layer of the STIstructure is silicon nitride. The sub-process may include using themethod for removing silicon oxide to etch the SiO₂ native oxide layer onthe hard mask layer of the STI structure; and controlling an etchingselectivity of the SiO₂ native oxide layer over a STI HARP deposition toremove the SiO₂ native oxide layer with an increased speed and avoidexcessive etching of the STI HARP deposition.

FIGS. 6A and 6B respectively illustrate schematics of a device having anative oxide layer and a device after removing the native oxide layeraccording to various disclosed embodiments of the present disclosure.

As shown in FIG. 6A, the integrated circuit manufacturing process mayuse Si₃N₄ as the hard mask layer of the STI structure, and a H₃PO₄ wetprocess may be required to remove the hard mask layer. However, thewafer with the hard mask layer may be naturally oxidized on the surfaceof the Si₃N₄ layer to form a dense SiO₂ layer after being placed in theair for a period of time, and the SiO₂ native oxide layer may be removedfirst before removing Si₃N₄. If the H₃PO₄ wet process, which is used toremove the hard mask layer, is used to remove the SiO₂, the removingrate of SiO₂ may be very slow. Furthermore, the STI HARP deposition inFIG. 6A may be the SiO₂ layer deposited by the CVD process, and the SiO₂layer may have a low density and be easily removed. When the SiO₂ nativeoxide layer on the surface of Si₃N₄ layer is removed, the removal amountof the STI HARP deposition may need to be controlled well, that is, theetching selectivity of the SiO₂ native oxide layer on the surface ofSi₃N₄ with respect to the STI HARP deposition may need to be controlled,which may ensure the step height of the STI structure (e.g., the STIstructure height which is higher than the substrate surface). The stepheight of the STI structure may affect the electrical properties of thedevice, so the step height of the STI structure may not be too high ortoo low.

Therefore, it is necessary to use the method of the present disclosureto remove the SiO₂ native oxide layer on the surface of Si₃N₄. FIG. 6Billustrates the device morphology after removing the SiO₂ native oxidelayer on the surface of Si₃N₄. In one embodiment, the processing stepsof the method for removing the silicon oxide provided by the presentdisclosure may be similar to the above-mentioned embodiments, which maynot be described in detail herein.

The method of the present disclosure may use a high-pressure process,which may improve the etching selectivity of the SiO₂ native oxide layeron the surface of Si₃N₄ with respect to the STI HARP deposition.Therefore, the SiO₂ native oxide layer on the surface of Si₃N₄ may beremoved quickly and may also avoid the excessive etching of STI HARPdeposition, thereby better controlling the step height of the STIstructure. Furthermore, when the SiO₂ native oxide layer on the surfaceof Si₃N₄ is removed, the method of the present disclosure may notgenerate solid reaction products, so the problem that the reactionproducts clog the small voids may be avoided, thereby improving thecleaning efficiency on the small voids and also capacity.

Embodiment 3: Integrated Circuit Pad Oxide Layer Removal

In one embodiment, the integrated circuit manufacturing process mayinclude a sub-process for removing a SiO₂ pad oxide layer formed byoxidizing a substrate surface using a heating method, where the padoxide layer is a buffer layer of a hard mask layer of a STI structurewhich is silicon nitride. The sub-process may include using the methodfor removing silicon oxide to etch the pad oxide layer; and controllingan etching selectivity of the pad oxide layer over a STI HARP depositionto remove the pad oxide layer with an increased speed and avoidexcessive etching of the STI HARP deposition.

FIGS. 7A and 7B respectively illustrate schematics of a device having apad oxide layer and a device after removing the pad oxide layeraccording to various disclosed embodiments of the present disclosure.

As shown in FIG. 7A, the pad oxide layer may be used as the buffer layerof the STI structure hard mask layer Si₃N₄ and may be the SiO₂ layerformed by thermally oxidizing the substrate surface by a tube furnacemethod, where the thickness may be determined according to differentprocesses (e.g., the thickness of the SiO₂ layer may be about 50 Å usinga 28 nm process). The pad oxide layer may need to be removed before asubsequent process. Furthermore, the STI HARP deposition in FIG. 7A maybe the SiO₂ layer deposited by the CVD process, and the SiO₂ layer mayhave a low density. When the pad oxide layer is required to be removed,the removal amount of the STI HARP deposition may need to be controlled,that is, the etching selectivity of the pad oxide layer with respect tothe STI HARP deposition may need to be controlled, which may remove thepad oxide layer quickly and may avoid excessive etching of the STI HARP,thereby ensuring the step height of the STI structure.

Therefore, it is necessary to use the method of the present disclosureto remove the pad oxide layer. FIG. 7B illustrates the device morphologyafter removing the pad oxide layer by the method of the presentdisclosure. In one embodiment, the processing steps of the method forremoving the silicon oxide provided by the present disclosure may besimilar to the above-mentioned embodiments, which may not be describedin detail herein.

The method of the present disclosure may use a high-pressure process,which may improve the etching selectivity of the pad oxide layer withrespect to the STI HARP deposition. Therefore, the pad oxide layer maybe removed quickly and may also avoid the excessive etching of STI HARP,thereby controlling the step height of the STI structure. Furthermore,when the pad oxide layer is removed, the method of the presentdisclosure may not generate solid reaction products, so the processefficiency and capacity may be improved, and problems, such as formingdivots due to the wet etching process which may affect electricalproperties, may be avoided.

Embodiment 4: Removing the Native Oxide Layer Before Depositing SiliconGermanium (SiGe)

In one embodiment, the integrated circuit manufacturing process mayinclude a sub-process for removing a SiO₂ native oxide layer on asilicon substrate before depositing silicon germanium. The sub-processmay include using the method for removing silicon oxide to etch the SiO₂native oxide layer on the silicon substrate; and controlling an etchingselectivity of the SiO₂ native oxide layer over polysilicon to removethe SiO₂ native oxide layer with an increased speed and avoid excessivedamage to the silicon substrate.

FIGS. 8A and 8B respectively illustrate schematics of a device having anative oxide layer and a device after removing the native oxide layeraccording to various disclosed embodiments of the present disclosure.

As shown in FIG. 8A, after pre-etching on the Si substrate for asubsequent SiGe deposition, the Si substrate in the etching region maybe exposed to the air and be naturally oxidized, and the native oxidelayer may cause problems such as the electrical property failure of thedevice, etc. The native oxide layer must be removed before depositingSiGe, and the Si substrate may not be damaged when the SiO₂ is removed.That is, the etching selectivity of the SiO₂ native layer to thepolysilicon (e.g., the Si substrate) may be well controlled.

Therefore, it is necessary to use the method of the present disclosureto remove the SiO₂ native oxide layer. FIG. 8B illustrates the devicemorphology after removing the SiO₂ native oxide layer by the method ofthe present disclosure. In one embodiment, the processing steps of themethod for removing the silicon oxide provided by the present disclosuremay be similar to the above-mentioned embodiments, which may not bedescribed in detail herein.

The method of the present disclosure may use a high-pressure process,which may improve the etching selectivity of the SiO₂ native layer tothe polysilicon, thereby removing the SiO₂ native oxide layer quicklyand also reducing the damage to gates and the Si substrate. Furthermore,when the SiO₂ native oxide layer is removed, the method of the presentdisclosure may not generate solid reaction products, so the problemsthat the solid products may be generated in the conventional technologyand the Si substrate may be re-oxidized in the high-temperaturesublimation process of the solid reaction products may be avoided.Therefore, the method for removing the silicon oxide provided by thepresent disclosure may be applied in the integrated circuitmanufacturing process, which may not only improve the process efficiencyand capacity and may also improve the device performance.

Embodiment 5: Removing the Native Oxide Layer Before Depositing Silicide

In one embodiment, the integrated circuit manufacturing process mayinclude a sub-process for removing a SiO₂ native oxide layer on asubstrate surface and a polysilicon gate surface before depositingsilicide. The sub-process may include using the method for removingsilicon oxide to etch the SiO₂ native oxide layer on the substratesurface and the polysilicon gate surface; and controlling an etchingselectivity of the SiO₂ native oxide layer over polysilicon to removethe SiO₂ native oxide layer with an increased speed and avoid excessivedamage to the silicon substrate.

FIGS. 1A and 3 respectively illustrate schematics of a device having anative oxide layer and a device after removing the native oxide layeraccording to a method of the present disclosure.

As shown in FIG. 1A, when the wafer is placed in the air, the surface ofthe Si substrate and the surface of the polysilicon gate may benaturally oxidized to form a dense SiO₂ layer. In order to avoid toolarge contact resistance between a contact electrode and the substrate,it may be required to remove the SiO₂ native oxide layer beforedepositing Ni or NiPt (about 5-10%) (NiPt formed in a subsequentprocess), however the Si substrate may not be damaged during the removalprocess. Furthermore, Si₃N₄, which may be used as insulating spacers onboth sides of the polysilicon gate, may not be damaged when removing theSiO₂ native oxide layer.

Therefore, it is necessary to use the method of the present disclosureto remove the SiO₂ native oxide layer. FIG. 3 illustrates the devicemorphology after removing the SiO₂ native oxide layer by the method ofthe present disclosure. In one embodiment, the processing steps of themethod for removing the silicon oxide provided by the present disclosuremay be similar to the above-mentioned embodiments, which may not bedescribed in detail herein.

The method of the present disclosure may use a high-pressure process,which may improve the etching selectivity of the SiO₂ native layer toSi₃N₄ and the Si substrate, thereby removing the SiO₂ native oxide layeron the surface of the Si substrate and the surface of the polysilicongate quickly, reducing the damage to the polysilicon gate and the Sisubstrate, and also avoiding problems such as reduced sizes of theinsulating spacers and increased leakage rate, etc. Furthermore, whenthe SiO₂ native oxide layer is removed, the method of the presentdisclosure may not generate solid reaction products, so it may avoid theproblems that the SiO₂ removal efficiency at the bottom of the voids dueto the presence of the solid reaction products in the conventionaltechnology may be low and the Si substrate may be re-oxidized in thehigh-temperature sublimation process of the solid reaction products.Therefore, the method for removing the silicon oxide provided by thepresent disclosure may be applied in the integrated circuitmanufacturing process, which may not only improve the process efficiencyand capacity and may also improve the device performance.

Embodiment 6: STI HARP Oxide Recess Etching

In one embodiment, the integrated circuit manufacturing process mayinclude a STI recess sub-process in a 2-dimensional NAND memorymanufacturing process, where the NAND memory includes floating gates anddense pattern region STI HARP depositions in a dense pattern region, andcontrol switch gates and sparse pattern region STI HARP depositions in asparse pattern region; the floating gates and the control switch gatesare made of polysilicon; the dense pattern region STI HARP depositionsand the sparse pattern region STI HARP depositions are made of siliconoxide. The sub-process may include using the method for removing siliconoxide to etch the dense pattern region STI HARP depositions and thesparse pattern region STI HARP depositions; and controlling an etchingselectivity of the STI HARP deposition over the floating gate or thecontrol switch gate to remove the STI HARP depositions with an increasedspeed and avoid excessive damage to the floating gates and the controlswitch gates.

FIGS. 9A and 9B respectively illustrate schematics of an integratedcircuit device having oxide recesses and an effect of removing siliconoxide of a device according to various disclosed embodiments of thepresent disclosure.

As shown in FIG. 9A, the STI recess process in one embodiment may be aprocess in a 2-dimensional NAND manufacturing process, and NAND is amemory device. In FIG. 9A, the dense pattern region on the left side maybe a memory region of the device, including the floating gates (e.g.,dark bars in the dense pattern region which may be polysilicon) and thedense pattern region STI HARP depositions (e.g., light bars in the densepattern region which may be silicon oxide); and the sparse patternregion on the right side may be a control region, including source/drainselective control switch gates (e.g., dark bars in the sparse patternregion which may be polysilicon, hereinafter referred to as “controlswitch gates”) and the sparse pattern region STI HARP depositions (e.g.,light bars in the sparse pattern region which may be silicon oxide). Inthe STI recess process, the removal amount of the STI HARP deposition inthe dense pattern region and the sparse pattern region may need to beconsistent.

Therefore, it is necessary to use the method of the present disclosureto remove the STI HARP deposition. FIG. 9B illustrates the devicemorphology after removing silicon oxide (STI HARP deposition) by themethod of the present disclosure. In one embodiment, the processingsteps of the method for removing the silicon oxide provided by thepresent disclosure may be similar to the above-mentioned embodiments,which may not be described in detail herein.

The method of the present disclosure may use a high-pressure process,which may improve the etching selectivity of the STI HARP depositionwith respect to the floating gate or with respect to the source/drainselective control switch gate, that is, the etching selectivity of theSiO₂ to the polysilicon, thereby removing the SiO₂ quickly and reducingthe damage to the polysilicon. Furthermore, when the SiO₂ layer isremoved, the method of the present disclosure may not generate solidreaction products, so it may eliminate the common problems in theconventional technology: that is, small voids may be easily to beclogged and difficult to clean due to the generation of the solidreaction products and the polysilicon may be re-oxidized in thehigh-temperature sublimation process of the solid reaction products.Therefore, the method for removing the silicon oxide provided by thepresent disclosure may be applied in the integrated circuitmanufacturing process, which may not only improve the process efficiencyand capacity, and may also improve the device performance.

The method and the manufacturing process for removing silicon oxide fromthe wafer according to the present disclosure have the followingadvantages.

The method provided by the present disclosure may use a gas phaseetching process to remove silicon oxide from the wafer. Compared withuse the wet etching process or the plasma dry etching process in theconventional technology, SiO₂ may be removed by chemical reactions andthere may be no solid reaction products in the removal process at thepresent disclosure. Therefore, the reaction products may be easilypumped out, thereby keeping chamber clean, and reducing or eveneliminating the particle contamination caused by the reaction products.Furthermore, since no solid reaction products are generated using themethod provided by the present disclosure, there is not necessary tovaporize or liquefy the solid reaction products by high-temperatureheating in the conventional technology and then discharge the vaporizedor liquefied reaction products. Therefore, high-temperature heating maynot be required, and the cooling step corresponding to the heating stepmay not be required accordingly. In such way, the reaction process maybe simple, which may not only improve the process efficiency andcapacity, but also save the process cost corresponding to the heatingstep and the cooling step.

Furthermore, the method provided by the present disclosure may use ahigh-pressure process (e.g., about 50 torr to 300 torr), which mayimprove etching selectivity of SiO₂ to Si₃N₄ (or polysilicon, HARPdeposition, etc.). In such way, the removal efficiency of silicon oxidefrom the wafer may be improved and the damage to the substrate may bereduced.

Similarly, the integrated circuit manufacturing process provided by thepresent disclosure may use the method provided by the present disclosureto remove silicon oxide from the wafer. Therefore, compared withintegrated circuit manufacturing process in the conventional technologyusing the wet etching process or the plasma etching process to removesilicon oxide, the integrated circuit manufacturing process provided bythe present disclosure may also improve the removal efficiency ofsilicon oxide, reduce the damage to the substrate, keep the chamberclean, reduce or even eliminate the particle contamination caused by thereaction products, and may also have the characteristics of simplereaction processes, high process efficiency and capacity, low costs,etc.

The method of the present disclosure has other features and advantages,which are apparent from the accompanying drawings and the embodimentsand will be described in detail in the accompanying drawings and theembodiments. The drawings and the detailed embodiments are used togetherto explain the principles of the present disclosure.

Those skilled in the art should understand that the above-mentioneddescription of the embodiments of the present disclosure is merelyintended to explain the advantages of the exemplary embodiments of thepresent disclosure and is not intended to limit the embodiments of thepresent disclosure.

The above-mentioned description of the embodiments of the presentdisclosure is exemplary, not exhaustive, and is not limited to theembodiments disclosed. Modifications and changes are apparent to thoseskilled in the art without departing from the scope of the presentdisclosure. The choice of terms used herein is intended to explain theprinciples of the various embodiments, actual applications ormodifications of the technology in the market, or to enable those ofordinary skill in the art to understand the embodiments disclosedherein.

What is claimed is:
 1. An integrated circuit manufacturing process,comprising: removing silicon oxide from a wafer in a vacuum environmentby a removal method, the removal method including: introducing adehydrated hydrogen fluoride gas and a dehydrated alcohol gas into aprocess chamber; mixing the dehydrated hydrogen fluoride gas with thedehydrated alcohol gas to generate gaseous etchants; allowing reactionsbetween the etchants and the wafer in the process chamber under apressure about 30 torr to about 300 torr maintained in the processchamber to improve an etching selectivity; after completing thereactions, pumping out reaction products from the process chamber, thereaction products including non-solid reaction products; and performinga subsequent process in the vacuum environment; and performing a shallowtrench isolation (STI) recess sub-process in a 2-dimensional NAND memorymanufacturing process, wherein: the NAND memory includes: floating gatesand STI high aspect ratio process (HARP) depositions in a dense patternregion, and control switch gates and STI HARP depositions in a sparsepattern region, the floating gates and the control switch gates beingmade of polysilicon, and the STI HARP depositions in the dense andsparse pattern regions being made of silicon oxide; and the sub-processincludes: applying the removal method to remove the STI HARP depositionsin the dense and sparse pattern regions; and controlling an etchingselectivity of the STI HARP depositions over the floating gate or thecontrol switch gate to remove the STI HARP depositions with an increasedspeed, thereby avoiding a damage to the floating gates and the controlswitch gates.
 2. The process according to claim 1, wherein: the pressurein the process chamber is about 200 torr.
 3. The process according toclaim 1, wherein: a temperature in the process chamber is about 20° C.to about 80° C.
 4. The process according to claim 3, wherein: thetemperature in the process chamber is about 40° C.
 5. The processaccording to claim 1, wherein: a flow rate of the dehydrated hydrogenfluoride gas is about 100 sccm to about 500 sccm; and a flow rate of thedehydrated alcohol gas is about 100 sccm to about 1000 sccm.
 6. Theprocess according to claim 5, wherein: the flow rate of the dehydratedhydrogen fluoride gas is about 150 sccm to about 225 sccm; and the flowrate of the dehydrated alcohol gas is about 200 sccm to about 450 sccm.7. The process according to claim 1, wherein: a ratio of the flow rateof the dehydrated hydrogen fluoride gas to the flow rate of thedehydrated alcohol gas is about (0.8˜1.2):1.
 8. The process according toclaim 7, wherein: the ratio of the flow rate of the dehydrated hydrogenfluoride gas to the flow rate of the dehydrated alcohol gas is about1:1.
 9. The process according to claim 1, wherein: the dehydratedalcohol gas is at least one of C1 to C8 monohydric alcohol gases. 10.The process according to claim 9, wherein: the dehydrated alcohol gas isat least one of methanol, ethanol, or isopropyl alcohol.